The TSMC 2013 Technology Symposium, held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies. Keynote speakers noted excellent yields and significant progress in 20nm planar, 16nm FinFET, and Chip-on-Wafer-on-Substrate (CoWoS) technologies, as well as promising development work with 10nm FinFET and true 3D-IC stacking.
Keynote speakers included Morris Chang, TSMC founder and CEO, who provided a semiconductor industry overview and company update (see blog post here). Subsequent keynote speeches were given by TSMC executives Jack Sun, Vice President of R&D and Chief Technology Officer; Cliff Hou, Vice President of R&D; and J.K. Wang, Vice President of Operations, 300mm Fabs.
While TSMC has four "flavors" of its 28nm process, there is one 20nm process, 20SoC. "20nm planar HKMG [high-k metal gate] technology has already passed risk production with a very high yield and we are preparing for a very steep ramp in two GIGAFABsTM," Sun said.
The next technology node is 10nm FinFET, which TSMC expects to release by the end of 2015. Sun said it will provide a "full node advancement" in power, performance and density compared to 16nm. What does that mean? Historically, Sun said, a new process node offers close to 2X density improvement, and can boost performance about 25%-30% at the same power. But with FinFETs, he said, TSMC can exceed that trend line and possibly provide 35% to 40% power savings at the same speed.
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