Designer of Microprocessor-Memory Chip Aims to Topple Memory and Power Walls
Since 2007, Fish and company have been engaged in the design and marketing of a novel CPU-DRAM technology, known as TOMI, which stands for Thread Optimized Multiprocessor. With TOMI, the company aims to do what no other chip maker has done before, namely embed a general-purpose processor in vanilla DRAM. The idea is to use the physical proximity of the CPU and memory, as well as extra-wide busses (4,096 bits, in the case of the first TOMI designs), to flatten the memory wall.
Whether you're talking about high performance computers, enterprise servers, or mobile devices, the two biggest impediments to application performance in computing today are the memory wall and the power wall. Venray Technology is aiming to knock down those walls with a unique approach that puts CPU cores and DRAM on the same die. The company has been in semi-stealth mode since it inception seven years ago, but is now trying to get the word out about its technology as it searches for a commercial buyer.
Since 2007, Fish and company have been engaged in the design and marketing of a novel CPU-DRAM technology, known as TOMI, which stands for Thread Optimized Multiprocessor. With TOMI, the company aims to do what no other chip maker has done before, namely embed a general-purpose processor in vanilla DRAM. The idea is to use the physical proximity of the CPU and memory, as well as extra-wide busses (4,096 bits, in the case of the first TOMI designs), to flatten the memory wall.
For these application profiles, performance basically flattened between four and eight cores, and actually declined beyond that. The problem was that as more cores were added, they were starved for the limited amount of memory bandwidth available, and after a certain point, the overhead of memory contention actually decreased performance. Prospective solutions, such as memory chip stacking (for example,Micron's Hybrid Memory Cube) are unproven and have yet to find their way into the commercial market.
The challenge of melding CPUs with DRAM is that microprocessors are much more complex beasts than memories, and as a result, are manufactured with entirely different semiconductor processes. Typically semiconductor logic require ten or more layers of material to be laid down on the die, compared to just three for DRAM. However, if a microprocessor can be designed much more simply, reducing the number and complexity of logic gate connections, it is possible to more or less flatten the layout and use just three layers.
That is the fundamental magic used by TOMI. Its second-generation design, named Borealis, consists of an 8-core RISC CPU built using the three-layer DRAM process. The CPU itself is made up of just 22 thousand transistors (not including cache and the memory controller), embedded in a 1 Gbit DRAM chip. On the 42nm process node, the CPU takes up just 14 percent of the die.
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