Intel has taken the wraps off its next chip technology, a 22nm process utilizing a new 3D trigate architecture promising faster speeds and big power savings, which will ramp to volume manufacturing later this year. Performance and power improvements in the Moore's Law-extending technology are "like nothing we've seen before [...] far exceed[ing] what we typically see from one process generation to the next," observed Intel Senior Fellow Mark Bohr.
Chipmakers have been tinkering for years with post-planar CMOS technology and visions of trigate architectures surrounding the channel. Whereas traditional 2D planar transistors form a conducting channel in the silicon under the gate electrode when on, the trigate vertical structure replaces the flat 2D stream with 3D fins, conducting and controlling channels on three sides to provide "fully depleted" operation. (Note that Intel doesn't use SOI, another viable yet expensive pathway to achieving full-depletion.) Multiple fins can be connected together to increase total drive strength.
Compared with 32nm planar chips, Intel's new 22nm trigates deliver >50% power reduction at constant performance, or a 37% performance increase at low voltage. The 22nm trigate circuits (364Mbit array size) incorporate 3rd-generation HKMG and the same transistor/interconnect features as on 22nm CPUs, but only add 2%-3% to process costs (vs. 10% for FDSOI), Intel says. First processors incorporating the trigate structure process (P1270), code-named "Ivy Bridge," are targeted for production ramp in 2H11 (maintaining the 2-year "tock" cadence for new tech generations); a 14nm version (P1272) is slated for 2013, and a 10nm one (P1274) in 2015.
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